IP개요 |
A bias quenching circuit in a CMOS technology integrated with single photon avalanche photodiodes (SPADs) for Geiger mode operation is developed. An improved bias quenching circuit is proposed to improve the performance of the quenching circuit and to reduce the circuit size as well. To maintain a constant quenching time regardless of breakdown voltage variation of SPADs, the calibration circuits is designed with a bias-correcting calibration capacitor and a current mirror circuit to pump a constant current during a measured time period depending the falling rate. The variation of the quenching time improves from 3.0 ns to 0.005 ns using the proposed quenching circuit. This architecture is based on mixed signal circuit of 0.35um CMOS process and the supply voltage is 3.3 V |