| IP개요 |
In this paper, a low-power 12-bit successive approximation register (SAR) resistance-to-digital converter (RDC) for resistive microsensors with a figure-of-merit (FoM) of 20 pJ/conversion-step is presented. In the conventional resistive analog front-end (AFE), two-step conversion schemes, including a resistance-to-voltage converter and a voltage-to-digital converter are generally used. The presented SAR RDC can directly convert the resistance changes to digital codes. The proposed SAR RDC consists of a comparing stage, and a SAR operating stage. The preamplifier of comparing stage implements a correlated double sampling (CDS) technique to improve the low-noise characteristic and reduce the low-frequency flicker (1/f) noise. The RDC is designed using SAR scheme to achieve low-power consumption. The SAR RDC achieves a wide input resistance range of 2 MΩ. The SAR RDC is implemented with a 0.18 μm standard complementary metal–oxide–semiconductor (CMOS) process. All functional blocks, including voltage and current references, oscillators, and timing generators, are integrated on the chip. The proposed RDC consumes 90 μW with 1.8 V power supply. The simulated SAR RDC achieve 12-bit resolution within a conversion time of 0.92 ms and a figure-of-merit (FoM) of 20 pJ/conversion-step. |
