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IP명 A Low-Power RF-to-BB-Current-Reuse Receiver Employing Simultaneous Noise and Input Matching and 1/f Noise Reduction for IoT Applications
Category Analog Application cellular
실설계면적 3.5㎛ X 3.5㎛ 공급 전압 1.2V
IP유형 Hard IP 동작속도 2.4GHz
검증단계 Simulation 참여공정 SS65-2002
IP개요 Abstract - A low-power low-noise RF-to-BB-current-reuse quadrature receiver employing simultaneous noise and input power matching and 1/f noise reduction technique is proposed for Internet of Things applications. The receiver shares bias current between a low-noise transconductor and a transimpedance amplifier with single supply voltage and employs a double-balanced current-mode passive mixer with 25% duty-cycle LO, thereby reducing power consumption. To improve noise performance in the direct-conversion or low-IF receiver, the proposed receiver architecture performs simultaneous noise and input power matching at the RF domain and 1/f noise reduction at the baseband domain. The presented prototype, implemented in 65-nm CMOS process, consumes 3.6 mW at a supply voltage of 1.8 V. It achieves a voltage gain of 42.5 dB, a NF of 1.94 dB, S11 of less than -10 dB, and an IIP3 of –26.2 dBm.
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