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IP Library

홈 | MPW / CDC | IP Library

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IP명 Single-Stage Rail-to-Rail Amplifier with Positive Feedback Loops
Category Analog Application Analog Driving Buffer
실설계면적 5㎛ X 5㎛ 공급 전압 1.8V
IP유형 Hard IP 동작속도 1MHz
검증단계 Simulation 참여공정 HM(상시모집)
IP개요 This rail-to-rail output class-AB single-stage amplifier is designed for display applications. To overcome weaknesses of the single-stage amplifier, a low DC gain and a low slew-rate, the proposed amplifier uses different-ratio current-mirrors (DRCMs) and positive feedback loops (PFBs). In addition, the proposed amplifier can drive wide range of capacitive load (Co) owing to the single-stage structure. The prototype chip was fabricated in a 0.18 μm CMOS technology for a power supply of 1.8V.
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