| IP명 | A 800MHz to 1.066GHz All Digital Delay Locked Loop With SAR Algorithm for LPDDR3 and DDR3 | ||
|---|---|---|---|
| Category | Analog | Application | Memory |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | Soft IP | 동작속도 | 1066MHz |
| 검증단계 | Silicon | 참여공정 | SS65-1901 |
| IP개요 | The proposed architecture has fast locking through SAR algorithm and fast locking through coarse locking, simplified structure for counter and offset calibration BBPD. The proposed architecture can reduce the locking cycle due to the SAR algorithm and coarse operation in the paper reported recently as a DLL applied to DDR3 and LPDDR3 | ||
- 레이아웃 사진 -
|
|||