| IP개요 |
In this paper, we propose the lossless decompression accelerator based on Inflate algorithm. We will aim to design the Inflate core that decodes the Deflate format and has appropriate trade-off. The Inflate core enhances the processing speed of the Inflate process by means of pipelining and the specified bitwise operation. The accelerator with the bus interface can be combined as any system peripheral to reduce the workload of the main processor. In order to construct the verification environment, we integrate the system that consists of the embedded processor, the proposed accelerator which verified on Xilinx FPGA, a peripheral for communication, and On-chip RAM to store the input stream. Finally, we will fabricate the system with Samsung 65 nm RF CMOS technology. Our design is operated in 3.3V, 100MHz. Our circuit type is Digital |
