mem_fifo Project Status (10/15/2013 - 10:32:11)
Project File: mem_fifo.ise Current State: Programming File Generated
Module Name: mem_test
  • Errors:
No Errors
Target Device: xc3s1000-4ft256
  • Warnings:
124 Warnings
Product Version: ISE 10.1 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
mem_fifo Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 68 15,360 1%  
Number of 4 input LUTs 178 15,360 1%  
Logic Distribution     
Number of occupied Slices 98 7,680 1%  
    Number of Slices containing only related logic 98 98 100%  
    Number of Slices containing unrelated logic 0 98 0%  
Total Number of 4 input LUTs 188 15,360 1%  
    Number used as logic 178      
    Number used as a route-thru 10      
Number of bonded IOBs
Number of bonded 87 173 50%  
Number of RAMB16s 8 24 33%  
Number of BUFGMUXs 1 8 12%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentȭ 10 15 10:31:48 20130121 Warnings1 Info
Translation ReportCurrentȭ 10 15 10:31:52 201301 Warning0
Map ReportCurrentȭ 10 15 10:31:55 201302 Warnings2 Infos
Place and Route ReportCurrentȭ 10 15 10:32:03 2013003 Infos
Static Timing ReportCurrentȭ 10 15 10:32:05 2013003 Infos
Bitgen ReportCurrentȭ 10 15 10:32:10 2013001 Info

Date Generated: 10/15/2013 - 10:32:11
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