mem_fifo Project Status (10/15/2013 - 10:32:11) | |||
Project File: | mem_fifo.ise | Current State: | Programming File Generated |
Module Name: | mem_test |
|
No Errors |
Target Device: | xc3s1000-4ft256 |
|
124 Warnings |
Product Version: | ISE 10.1 - Foundation Simulator |
|
All Signals Completely Routed |
Design Goal: | Balanced |
|
All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
|
0 (Timing Report) |
mem_fifo Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 68 | 15,360 | 1% | ||
Number of 4 input LUTs | 178 | 15,360 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 98 | 7,680 | 1% | ||
Number of Slices containing only related logic | 98 | 98 | 100% | ||
Number of Slices containing unrelated logic | 0 | 98 | 0% | ||
Total Number of 4 input LUTs | 188 | 15,360 | 1% | ||
Number used as logic | 178 | ||||
Number used as a route-thru | 10 | ||||
Number of bonded IOBs | |||||
Number of bonded | 87 | 173 | 50% | ||
Number of RAMB16s | 8 | 24 | 33% | ||
Number of BUFGMUXs | 1 | 8 | 12% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ȭ 10 15 10:31:48 2013 | 0 | 121 Warnings | 1 Info | |
Translation Report | Current | ȭ 10 15 10:31:52 2013 | 0 | 1 Warning | 0 | |
Map Report | Current | ȭ 10 15 10:31:55 2013 | 0 | 2 Warnings | 2 Infos | |
Place and Route Report | Current | ȭ 10 15 10:32:03 2013 | 0 | 0 | 3 Infos | |
Static Timing Report | Current | ȭ 10 15 10:32:05 2013 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | ȭ 10 15 10:32:10 2013 | 0 | 0 | 1 Info |