syn Project Status | |||
Project File: | syn.ise | Current State: | Programming File Generated |
Module Name: | top_uart_fifo |
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Target Device: | xc3s1000-4ft256 |
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Product Version: | ISE 10.1 - Foundation Simulator |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
syn Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 368 | 15,360 | 2% | ||
Number of 4 input LUTs | 899 | 15,360 | 5% | ||
Logic Distribution | |||||
Number of occupied Slices | 509 | 7,680 | 6% | ||
Number of Slices containing only related logic | 509 | 509 | 100% | ||
Number of Slices containing unrelated logic | 0 | 509 | 0% | ||
Total Number of 4 input LUTs | 919 | 15,360 | 5% | ||
Number used as logic | 867 | ||||
Number used as a route-thru | 20 | ||||
Number used for Dual Port RAMs | 32 | ||||
Number of bonded IOBs | |||||
Number of bonded | 74 | 173 | 42% | ||
Number of RAMB16s | 1 | 24 | 4% | ||
Number of BUFGMUXs | 2 | 8 | 25% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ¼ö 10 16 13:21:13 2013 | ||||
Translation Report | Current | ¼ö 10 16 13:21:17 2013 | ||||
Map Report | Current | ¼ö 10 16 13:21:22 2013 | ||||
Place and Route Report | Current | ¼ö 10 16 13:21:28 2013 | ||||
Static Timing Report | Current | ¼ö 10 16 13:21:30 2013 | ||||
Bitgen Report | Current | ¼ö 10 16 13:21:35 2013 |