syn Project Status
Project File: syn.ise Current State: Programming File Generated
Module Name: top_uart_fifo
  • Errors:
 
Target Device: xc3s1000-4ft256
  • Warnings:
 
Product Version: ISE 10.1 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
syn Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 368 15,360 2%  
Number of 4 input LUTs 899 15,360 5%  
Logic Distribution     
Number of occupied Slices 509 7,680 6%  
    Number of Slices containing only related logic 509 509 100%  
    Number of Slices containing unrelated logic 0 509 0%  
Total Number of 4 input LUTs 919 15,360 5%  
    Number used as logic 867      
    Number used as a route-thru 20      
    Number used for Dual Port RAMs 32      
Number of bonded IOBs
Number of bonded 74 173 42%  
Number of RAMB16s 1 24 4%  
Number of BUFGMUXs 2 8 25%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent¼ö 10 16 13:21:13 2013   
Translation ReportCurrent¼ö 10 16 13:21:17 2013   
Map ReportCurrent¼ö 10 16 13:21:22 2013   
Place and Route ReportCurrent¼ö 10 16 13:21:28 2013   
Static Timing ReportCurrent¼ö 10 16 13:21:30 2013   
Bitgen ReportCurrent¼ö 10 16 13:21:35 2013   

Date Generated: 10/16/2013 - 13:36:49
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