Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 

 
Software Version and Target Device
Product Version: ISE:10.1 (Foundation Simulator) Target Family: spartan3
OS Platform: NT Target Device: xc3s1000
Project ID (random number) 6445.16927.4 Target Package: ft256
Registration ID 1B62AJFMAGS2XTU10FJW0HB5Y Target Speed: -4
Date Generated 수 10 16 16:37:55 2013
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Multiplexers=11
  • 1-bit 4-to-1 multiplexer=2
  • 1-bit 8-to-1 multiplexer=8
  • 3-bit 16-to-1 multiplexer=1
Registers=331
  • Flip-Flops=331
Comparators=7
  • 3-bit comparator greater=1
  • 5-bit comparator equal=1
  • 5-bit comparator greatequal=1
  • 5-bit comparator greater=2
  • 6-bit comparator less=2
ROMs=4
  • 16x10-bit ROM=1
  • 16x8-bit ROM=1
  • 4x3-bit ROM=1
  • 4x4-bit ROM=1
RAMs=3
  • 1024x8-bit single-port block RAM=1
  • 16x8-bit dual-port distributed RAM=2
Counters=4
  • 10-bit down counter=1
  • 16-bit down counter=1
  • 8-bit down counter=2
Xors=5
  • 1-bit xor2=3
  • 1-bit xor5=1
  • 1-bit xor9=1
Adders/Subtractors=13
  • 16-bit subtractor=1
  • 18-bit adder=1
  • 3-bit subtractor=2
  • 4-bit adder=4
  • 4-bit subtractor=1
  • 5-bit addsub=2
  • 5-bit subtractor=1
  • 9-bit subtractor=1
MiscellaneousStatistics
  • AGG_BONDED_IO=74
  • AGG_IO=74
  • AGG_SLICE=508
  • NUM_4_INPUT_LUT=919
  • NUM_BONDED_IOB=74
  • NUM_BUFGMUX=1
  • NUM_CYMUX=83
  • NUM_DP_RAM=32
  • NUM_LUT_RT=20
  • NUM_RAMB16=1
  • NUM_SLICEL=486
  • NUM_SLICEM=22
  • NUM_SLICE_FF=367
  • NUM_XOR=76
NetStatistics
  • NumNets_Active=1052
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=2
  • NumNodesOfType_Active_BRAMDUMMY=8
  • NumNodesOfType_Active_CLKPIN=286
  • NumNodesOfType_Active_CNTRLPIN=433
  • NumNodesOfType_Active_DOUBLE=1815
  • NumNodesOfType_Active_DUMMY=3033
  • NumNodesOfType_Active_DUMMYBANK=5
  • NumNodesOfType_Active_DUMMYESC=15
  • NumNodesOfType_Active_GLOBAL=79
  • NumNodesOfType_Active_HFULLHEX=31
  • NumNodesOfType_Active_HLONG=4
  • NumNodesOfType_Active_HUNIHEX=172
  • NumNodesOfType_Active_INPUT=3330
  • NumNodesOfType_Active_IOBOUTPUT=15
  • NumNodesOfType_Active_OMUX=1077
  • NumNodesOfType_Active_OUTPUT=963
  • NumNodesOfType_Active_PREBXBY=780
  • NumNodesOfType_Active_VFULLHEX=112
  • NumNodesOfType_Active_VLONG=43
  • NumNodesOfType_Active_VUNIHEX=136
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=74
  • IOB_INBUF=15
  • IOB_OUTBUF=67
  • IOB_PAD=74
  • RAMB16=1
  • RAMB16_RAMB16=1
  • RAMB16_RAMB16A=1
  • SLICEL=486
  • SLICEL_C1VDD=34
  • SLICEL_C2VDD=28
  • SLICEL_CYMUXF=45
  • SLICEL_CYMUXG=38
  • SLICEL_F=442
  • SLICEL_F5MUX=58
  • SLICEL_F6MUX=10
  • SLICEL_FFX=226
  • SLICEL_FFY=138
  • SLICEL_G=433
  • SLICEL_GNDF=11
  • SLICEL_GNDG=8
  • SLICEL_VDDG=2
  • SLICEL_XORF=38
  • SLICEL_XORG=38
  • SLICEM=22
  • SLICEM_F=22
  • SLICEM_F5MUX=6
  • SLICEM_F6MUX=6
  • SLICEM_FFY=3
  • SLICEM_G=22
  • SLICEM_WSGEN=16
 
Configuration Data
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
IOB_PAD
  • DRIVEATTRBOX=[12:67]
  • IOATTRBOX=[LVCMOS33:74]
  • SLEW=[SLOW:67]
RAMB16_RAMB16A
  • PORTA_ATTR=[2048X9:1]
  • WRITEMODEA=[NO_CHANGE:1]
SLICEL_FFX
  • FFX_INIT_ATTR=[INIT0:204] [INIT1:22]
  • FFX_SR_ATTR=[SRLOW:204] [SRHIGH:22]
  • LATCH_OR_FF=[FF:226]
  • SYNC_ATTR=[ASYNC:226]
SLICEL_FFY
  • FFY_INIT_ATTR=[INIT0:121] [INIT1:17]
  • FFY_SR_ATTR=[SRLOW:121] [SRHIGH:17]
  • LATCH_OR_FF=[FF:138]
  • SYNC_ATTR=[ASYNC:138]
SLICEM_F
  • F_ATTR=[DUAL_PORT:16]
  • LUT_OR_MEM=[LUT:6] [RAM:16]
SLICEM_FFY
  • FFY_INIT_ATTR=[INIT0:3]
  • FFY_SR_ATTR=[SRLOW:3]
  • LATCH_OR_FF=[FF:3]
  • SYNC_ATTR=[ASYNC:3]
SLICEM_G
  • G_ATTR=[DUAL_PORT:16]
  • LUT_OR_MEM=[LUT:6] [RAM:16]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=15
  • O1=67
  • PAD=74
  • T1=32
IOB_INBUF
  • IN=15
  • OUT=15
IOB_OUTBUF
  • IN=67
  • OUT=67
  • TRI=32
IOB_PAD
  • PAD=74
RAMB16
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DIA0=1
  • DIA1=1
  • DIA2=1
  • DIA3=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIPA0=1
  • DOA0=1
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=1
  • SSRA=1
  • WEA=1
RAMB16_RAMB16
  • ADDRA=1
  • DIA=1
  • DOA=1
RAMB16_RAMB16A
  • ADDRA=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DIA=1
  • DIA0=1
  • DIA1=1
  • DIA2=1
  • DIA3=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIPA0=1
  • DOA=1
  • DOA0=1
  • DOA1=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • ENA=1
  • SSRA=1
  • WEA=1
SLICEL
  • BX=84
  • BY=47
  • CE=112
  • CIN=38
  • CLK=266
  • COUT=38
  • F1=440
  • F2=409
  • F3=360
  • F4=264
  • F5=20
  • FX=3
  • FXINA=10
  • FXINB=10
  • G1=431
  • G2=403
  • G3=330
  • G4=231
  • SR=266
  • X=216
  • XB=1
  • XQ=226
  • Y=281
  • YQ=138
SLICEL_C1VDD
  • 1=34
SLICEL_C2VDD
  • 1=28
SLICEL_CYMUXF
  • 0=45
  • 1=45
  • OUT=45
  • S0=45
SLICEL_CYMUXG
  • 0=36
  • 1=38
  • OUT=38
  • S0=38
SLICEL_F
  • A1=440
  • A2=409
  • A3=360
  • A4=264
  • D=442
SLICEL_F5MUX
  • F=58
  • G=58
  • OUT=58
  • S0=58
SLICEL_F6MUX
  • 0=10
  • 1=10
  • OUT=10
  • S0=10
SLICEL_FFX
  • CE=92
  • CK=226
  • D=226
  • Q=226
  • SR=226
SLICEL_FFY
  • CE=62
  • CK=138
  • D=138
  • Q=138
  • SR=138
SLICEL_G
  • A1=431
  • A2=403
  • A3=330
  • A4=231
  • D=433
SLICEL_GNDF
  • 0=11
SLICEL_GNDG
  • 0=8
SLICEL_VDDG
  • 1=2
SLICEL_XORF
  • 0=38
  • 1=38
  • O=38
SLICEL_XORG
  • 0=38
  • 1=38
  • O=38
SLICEM
  • BX=6
  • BY=22
  • CLK=19
  • F1=22
  • F2=22
  • F3=22
  • F4=16
  • F5=6
  • FX=3
  • FXINA=6
  • FXINB=6
  • G1=22
  • G2=22
  • G3=22
  • G4=16
  • SR=19
  • X=16
  • Y=3
  • YQ=3
SLICEM_F
  • A1=22
  • A2=22
  • A3=22
  • A4=16
  • D=22
  • DI=16
  • WF1=16
  • WF2=16
  • WF3=16
  • WF4=16
  • WS=16
SLICEM_F5MUX
  • F=6
  • G=6
  • OUT=6
  • S0=6
SLICEM_F6MUX
  • 0=6
  • 1=6
  • OUT=6
  • S0=6
SLICEM_FFY
  • CK=3
  • D=3
  • Q=3
  • SR=3
SLICEM_G
  • A1=22
  • A2=22
  • A3=22
  • A4=16
  • D=6
  • DI=16
  • WG1=16
  • WG2=16
  • WG3=16
  • WG4=16
  • WS=16
SLICEM_WSGEN
  • CK=16
  • WE=16
  • WSF=16
  • WSG=16
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
>
Software Quality
Run Statistics
ProgramRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_compxlibgui 1 1 0 0 0 0 0
bitgen 323 322 0 0 0 0 0
compxlib 1 1 0 0 0 0 0
edif2ngd 117 117 0 0 0 0 0
map 344 339 0 0 0 0 0
netgen 140 138 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngcbuild 110 110 0 0 0 0 0
ngdbuild 402 400 0 0 0 0 0
par 339 335 4 0 0 0 0
trce 332 332 0 0 0 0 0
xst 582 569 0 0 0 0 0
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=Modelsim-SE Mixed
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=Verilog
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_UCF=1 FILE_VERILOG=17
PROP_DevDevice=xc3s1000 PROP_DevFamily=Spartan3
PROP_DevPackage=ft256 PROP_DevSpeed=-4
PROP_FitterReportFormat=HTML PROP_UserConstraintEditorPreference=Constraints Editor
Project duration(days)=0