| IP개요 |
This paper presents a noise shaping (NS) successive approximation register (SAR) analog to digital converter (ADC). Conventional NS SAR ADCs commonly use passive integrator based on charge sharing technique which contains multiple switches and integrating capacitors. Therefore, subthreshold leakage current from off-state transistor can degrade the noise transfer function and increase harmonic distortion (HD) which leads to low performance of the NS SAR ADC. Fabricated in 65nm CMOS process, designed ADC achieved 62.8dB of signal-to-noise-and-distortion-ratio and 76.0dB of spurious-free-dynamic-range with 5MS/s operation. |
