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IP Library

홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

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IP명 12-bit 2MSps RC Two-step Multi-Channel SAR-ADC with Conversion Time Modification Logic
Category Mixed Application Data Converter
실설계면적 4㎛ X 2㎛ 공급 전압 1V
IP유형 Hard IP 동작속도 10~20MHz
검증단계 Silicon 참여공정 SS28-2102
IP개요 In this work, a two-step SAR ADC is proposed applicable to high-speed CIS systems. The design techniques are as follows.
Firstly, to reduce the area, we use resistor DAC (RDAC) and capacitor DAC (CDAC) separately, and the resistor DAC applies a certain layout technique, called cross-connected layout method, to increase device matching.
Secondly, to resolve settling time issue by using resistor, bit-cycling time control logic and LSB correction logic have been implemented for enhancing sampling speed of the ADC.
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