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IP Library

홈 | MPW / CDC | IP Library

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IP명 Ultra-low-latency ordered statistic decoding architecture for B5G/6G URLLC IIOT networks
Category Digital Application Communication
실설계면적 4㎛ X 4㎛ 공급 전압 1.0V
IP유형 Hard IP 동작속도 200MHz
검증단계 Silicon 참여공정 SS28-2101
IP개요 This project newly proposes an ultra-low-latency ordered statistic decoding (OSD) architecture. To reduce the decoding latency of OSD, our architecture optimizes the Gaussian elimination and several condition computation with low resolution fixed-point arithmetic operation. Also, we uses the conventional BCH decoding architecture for early termination of the decoding. As a result, the proposed architecture is fabricated in 28nm CMOS process and this architecture can be realization of the OSD algorithm for B5G/6G URLLC IIOT networks
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