| IP개요 |
A low power high SFDR direct digital frequency synthesizer (DDFS) with improved digital decoder logic is proposed. In previous research, coarse phase-based consecutive fine amplitude grouping (C2FAG) scheme is employed as a digital decoding logic for reduce circuit complexity and power consumption. However, in order to increase the sinewave amplitude resolution, the complexity of the circuit increases exponentially due to the limitation of decoding logic, which uses a thermometer to create a phase. In this paper, the improved C2FAG (IC2FAG) is used to increase sinewave amplitude resolution and achieve a circuit complexity reduction. In MATLAB simulation, IC2FAG logic achieved spurious free dynamic range (SFDR). This work will be designed in 28 nm CMOS process. The DDFS can create 10-bit amplitude resolution sine-wave with simulated SFDR of 74.01 dBc DC to half at the reference clock frequency of 2.4 GHz. it occupies an active area of 0.032 mm2 with a total power dissipation of 56 mW. The FoM of this DDFS is 221425 GHz·2(SFDR/6)/W. |
