| IP명 | Analog Synapse-Based Neuromorphic System for Deep Neural Network Process | ||
|---|---|---|---|
| Category | Analog | Application | Neuromorphic |
| 실설계면적 | 9.5㎛ X 5㎛ | 공급 전압 | 1.8/5V |
| IP유형 | Hard IP | 동작속도 | 1.01MHz |
| 검증단계 | Silicon | 참여공정 | HM-2102 |
| IP개요 | It proposes synapse cells and Neuromorphic Architecture composed of CMOS. The proposed synapse cell ensures linearity and symmetry through current sources and switches. Neuromorphic Architecture can send updates and read pulses to drive these synapse cells. And it can also read value of synapse cells’ outputs. The proposed Neuromorphic architecture is manufactured by TSMC250 nm standard CMOS process with 1.8 V / 5 V supply voltage, with a total size of chips of 9.5mm X 5mm. |
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- 레이아웃 사진 -
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