| IP개요 |
This chip presented A 2.4GHz Reference-Sampling based Fractional-N PLL With Hybrid Phase-Interpolator. Reference-samping PLL(RSPLL) operate by sampling a reference signal as an output signal, thereby solving the trade-off problem between the sampling spur and jitter performnce caused by the isolation buffer in the existing sub-sampling PLL(SSPLL). In addition, since it has a wide locking range, a stable sampling circuit can be implemented. This chip a phase-locked loop that enables precise control of the output frequency based on the advantages of the RSPLL structure, has the advantages of structural simplicity and low power consumption, and presents additional logic for implementing the fractional operation of the circuit. Based on the structural advantages of the circuit proposed in this IP, it is expected that it can be applied to applications requiring multiple phases with low power. |
