회원가입로그인 ENGLISH naver youtube  

[외부공지] [홍보-채용] Synopsys사 A&MS Circuit Design Engineer 채용 안내 2021.11.19. 16:57
이경옥 (ky****)  

IC Design Education Center(IDEC)  

[홍보-채용] Synopsys사 A&MS Circuit Design Engineer 채용

Synopsys Korea 에서는 국내 반도체 IP 개발 연구소 설립 및 현지 인력 채용과 고객 지원을 위한 투자를 강화함에 따라 석사 이상 신입 위주로 채용을 예정하고 있습니다. 지원 희망 시, 아래 채용 공고 및 지원 방법을 참고해주시길 바랍니다.

[A&MS Circuit Design Engineer 채용 안내]

담당 업무
  • Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications.
  • Identify and refine circuit implementations to achieve optimal power, area and performance targets.
  • Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design.
  • Oversee physical layout to minimize the effect of parasitics, device stress and process variation.
  • Collaborate with digital RTL engineers on the verification of calibration, adaptation and control algorithms for analog circuits.
  • Present simulation data for peer and customer review.
  • Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design.
  • Document design features and test plans.
  • Consult on the electrical characterization of your circuit within the SerDes IP product.

 필수 역량 및
 자격 요건
  • Relevant experience or study background of SerDes/High-Speed analog design experience.
  • Familiarity with the transistor-level circuit design of fundamental analog and mixed-signal building blocks- sound CMOS design fundamentals.
  • Silicon-proven experience implementing circuits for analog and mixed-signal building blocks
  • Design experience with some of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
  • Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
  • Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
  • Experience with EDA tools for schematic entry, physical layout, and design verification.
  • Knowledge of SPICE simulators and simulation methods.
  • Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
  • Experience with TCL, Perl, C, Python, MATLAB.

지원을 희망하시는 경우, 아래의 연락처로 영문 이력서를 제출해주시길 바랍니다.

- 담당자 : 이천오 이사(cheono@synopsys.com)
- 지원 방법 : 영문 이력서 이메일을 통해 제출
- 지원 기한 : 상시 채용


담당 : 이경옥 (042-350-8533, kyungoklee@idec.or.kr)