A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces 2023.05.09. 19:05 Yuhwan Shin 논문번호 : 202303058 주저자 : Yuhwan Shin 소속 : KAIST 지도교수 : Jaehyouk Choi 전시담당자 : Yuhwan Shin(yuhwan.shin@kaist.ac.kr) 포스터 : 댓글 0 ↓
Yuhwan Shin
