| IP명 | Time-Multiplexed Chopped Neural Interface with Double Positive Feedback Loop Impedance Boosting | ||
|---|---|---|---|
| Category | Analog | Application | Neural Recording |
| 실설계면적 | 5㎛ X 3㎛ | 공급 전압 | 1.5/1.0V |
| IP유형 | Soft IP | 동작속도 | 5.12MHz |
| 검증단계 | Silicon | 참여공정 | HM-2301 |
| IP개요 | An 8-channel neural recording IC with time-multiplexing to interface with 64 input electrodes arranged in an 8x8 array configuration, with multiplexing switches outside the chip. The analog front-end includes a CCIA structure, with DSL and a manually set dual-positive feedback loop, followed by a PGA. The analog output is converted to digital using a ping-pong SAR ADC. A controller arranges the aggregated data for all 64 input electrodes to be output serially from the chip. | ||
- 레이아웃 사진 -
|
|||