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홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

IDEC에서 설계인력양성의 발판을 마련하겠습니다.

IP명 A 5.8 GHz DSRC Receiver RF Front-end for V2X Communication Systems
Category Analog Application cellular
실설계면적 4㎛ X 4㎛ 공급 전압 1.2V
IP유형 Hard IP 동작속도 5.8GHz
검증단계 Silicon 참여공정 SS28-2001
IP개요 In this paper, a RF front-end of the 5.8 GHz integrated CMOS dedicated short range communication (DSRC) receiver for Korea/Japan V2X Communication systems is presented. The receiver uses low-IF conversion architecture for high sensitivity and low-power consumption. To solve image problem in the low-IF receiver, 10 MHz IF and 40 MHz IF are chosen for Korean and Japanese DSRC standards, respectively, since they make no image signals exist in image band. A single-quadrature mixer with the proposed transconductor-type quadrature generator in RF signal path is also adopted which has accurate quadrature characteristic in 5.8 GHz frequency.
When the RF front-end of the integrated 5.8 GHz DSRC receiver is implemented using 28 nm CMOS technology, the receiver achieves the overall noise figure of less than 5 dB with image rejection ratio of more than 30 dB. The RF front-end of the 5.8 GHz DSRC receiver dissipates 45 mA with 1.2 V supply voltage.
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