| IP개요 |
Phase change random access memory (PCRAM) has been emerged as a great potential memory device due to its excellent scalability, non-volatility, random accessibility. However, its read access time which is about two times larger than DRAM’s is a limiting factor to make DRAM/PCRAM hybrid memory performance being comparable to the original DRAM-only memory performance and decreasing read cell current (ICELL) due to cell scaling will increase read access time further. Besides, large process variation of CMOS limits yields of PCRAM. We propose a novel high speed sense amplifier for PCRAM to improve sensing time with being offset tolerant and insensitive to process variation of CMOS. The proposed sensing circuit will be implemented in 28 nm CMOS process. Since the PCRAM cell is not supported in this process, a full-CMOS macro cell to emulate the operation of a PCRAM cell will be designed to configure our PCRAM array. The estimated sensing time by using the proposed scheme is 18 ns, which indicates that the sensing time is reduced by as much as 58% as compared to the conventional. Transient simulation results of the proposed amplifier show outstanding improvement of sensing speed. |
