| IP명 | A Power- and Area-Efficient DFE Receiver | ||
|---|---|---|---|
| Category | Analog | Application | consumer electronics |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | Hard IP | 동작속도 | 5GHz |
| 검증단계 | Silicon | 참여공정 | SS065-1802 |
| IP개요 | –This paper describes a power and area efficient decision-feedback equalization (DFE) receiver in high-speed I/O interface. The proposed DFE receiver consists of a MUX-embedded summer and time-interleaving samplers to remove inter-symbol interference (ISI) efficiently. It can use a smaller number of DFE tap elements and summers than the conventional DFE receiver does, resulting in reduced power consumption and chip size. The performance evaluation is done in 65-nm CMOS process, whose simulation results indicate that the proposed DFE receiver operates at up to 10 Gb/s data rate. |
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