| IP개요 |
This paper proposes a fast-transient coarse-fine digital low-dropout regulator (D-LDO). The conventional D-LDO operates a coarse shift-register and a comparator at a fast clock in coarse mode when an overshoot or undershoot voltage occurs, for a fast-transient response. After coarse mode, it operates a fine shift-register at a slow clock for low power consumption in fine mode. However, the comparator operates at a fast clock for a low ripple voltage. The proposed D-LDO reduces the response time to a half of the conventional D-LDO, by using the proposed double edge-triggered comparator and by shifting the shift-register at the double edges of clocks. As a result, it reduces the overshoot and undershoot voltages. It also reduces the power consumption of the comparator in fine mode by using a slow clock instead of a fast clock. But, it still has a low ripple voltage due to the proposed comparator with a completion signal. The proposed D-LDO was implemented using a 65nm CMOS process. In the simulation, the settling time is reduced to 340ns from 880ns of the conventional D-LDO. The overshoot and undershoot voltages are reduced to 23mV and 37mV from 129mV and 127mV, respectively. The ripple voltage is 1.5mV and the current efficiency is 99.94%. |
