| IP명 | DRAM circuit | ||
|---|---|---|---|
| Category | Analog | Application | processing in memory |
| 실설계면적 | 3.8㎛ X 3.8㎛ | 공급 전압 | 1.8V |
| IP유형 | 동작속도 | 80000000Hz | |
| 검증단계 | Silicon | 참여공정 | MS180-1804 |
| IP개요 | In-DRAM processing circuit is able to reduce operation time and power consumption than the traditional CPU + MEMORY system in performing the complicated computation such as convolution. These benefits are gained by bitwise and parallel processing of the in-DRAM convolution circuit. To realize the in-DRAM circuit, an inter-bank processing circuit is proposed with bitwise summation/ a comparison circuit for performing convolution inside DRAM. Compared to the intra-bank bitwise operation, the inter-bank circuit can significantly reduce the power consumption and the number of row activation cycles to accomplish convolution. |
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- 레이아웃 사진 -
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