| IP개요 |
In this design, a single-ended duobinary transceiver for high-density memory interface is proposed. The proposed transceiver employs a duobinary crosstalk cancellation technique (XTC) by simple method. In addition, it employs pin-less ZQ calibration by using reflection voltage. The proposed ZQ calibration is an impedance matching method that does not require the conventional ZQ pin, thereby improving pin efficiency and contributing to the enhancement of bandwidth per unit area in memory interfaces. The prototype chip is planned to be fabricated with an area of 4mm x 4mm using a 28nm LPP process. |
