| IP개요 |
This proposal suggests a low-power asynchronous 10-bit 2-then-1b/cycle successive approximation register (SAR) analog-to-digital converter (ADC) architecture. By partially applying the 2b/cycle mode to only the higher-order bit conversions, the design aims to reduce both area and power consumption while sustaining a high conversion rate. Unlike conventional 2b/cycle conversion approaches that require two capacitive digital-to-analog converters (C-DACs) and multiple analog comparators, the proposed architecture leverages a digital-based time-domain reference to implement the 2-then-1b/cycle operation with only a single C-DAC and one analog comparator. Furthermore, the speed of 1b/cycle conversion for lower-order bits is enhanced through the integration of a dual-mode comparator, ensuring faster and more efficient conversion. |
