| IP개요 |
Recently, Ising-model-based hardware accelerators have gained large attention by mapping combinatorial optimization problems (COPs) onto an Ising Hamiltonian and searching for low-energy solutions through spin dynamics. However, previous digital Ising cores have exhibited dynamics that are largely deterministic after initialization, making the outcome sensitive to initial conditions and prone to trapping in local minima, especially for large-scale COPs. In this proposal, we aim to build a probabilistic Ising computing core using analog p-bits as fundamental computational elements that enable intrinsically stochastic updates that improve exploration and facilitate escape from local optima. In addition, unlike conventional synchronous digital Ising solvers that rely on iterative and discrete-time operations, the proposed mixed-signal architecture exploits continuous-time asynchronous dynamics to minimize latency and improve time-to-solution. To support high-fidelity mapping of large and complex COP benchmarks, we target an all-to-all coupling topology and a massively scalable architecture. We further improve solution quality and convergence behavior by increasing precision of coupling coefficients via a high-resolution weight storage/accumulation interface. To ensure robust run-to-run diversity and high-quality initialization, the core integrates a bias-robust TRNG to provide reliable seeding/re-seeding and optional noise injection. |
