| IP명 | High-Performance Single-Ended PAM-4 Transceiver with 2-Stack 4:1 Multiplexing Driver and Middle-Level Edge-Boosting FFE for Die-to-Die Communication | ||
|---|---|---|---|
| Category | Analog | Application | Chiplet, Memory |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 54GHz |
| 검증단계 | Silicon | 참여공정 | SS028-2601 |
| IP개요 | In this design, a single-ended PAM-4 transceiver for die-to-die communication is proposed. The proposed transceiver employs a 2-stack 4:1 multiplexing driver to eliminate full-rate internal nodes, thereby extending the overall bandwidth and improving power efficiency. In addition, it downsizes the main driver to minimize static current consumption and employs a middle-level edge-boosting techniques. This proposed technique is an effective equalization method that selectively improves the slew rate of the middle voltage levels, thereby enhancing signal integrity and contributing to the maximization of bandwidth per unit area in die-to-die communications. The prototype chip is planned to be fabricated with an area of 4mm x 4mm using a 28nm LPP process. |
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