| IP개요 |
With the growing demand for high-performance computing in data centers and automotive applications, there is an increasing need for power delivery solutions that provide greater power capability, higher efficiency, and faster response. However, it is still challenging to robustly control a DSD converter to achieve fast transient responses. This paper proposes a DSD buck converter topology that incorporates a dual-phase charging technique to mitigate transient ripple challenges. The dual-phase charging concept enables a faster energy ramp-up during rapid transient events. The proposed design achieves up to a 2% efficiency improvement compared to conventional architectures, with modeling results closely matching previously reported values—indicating that the outcomes are both reliable and consistent. By employing an effective control strategy, the design maintains voltage droop below 100mV. The buck converter will be fabricated using Samsung's 130nm BCDMOS technology, with an expected peak efficiency of 92%. This design will be entirely implemented as a mixed-signal circuit, utilizing both transistor-level design and a standard cell library. |
