| IP명 | A Wide Load Range and High Power Supply Rejection NMOS LDO with Load Current Sensing | ||
|---|---|---|---|
| Category | Mixed | Application | SoC PMIC |
| 실설계면적 | 3.55㎛ X 3.55㎛ | 공급 전압 | 5V |
| IP유형 | Hard IP | 동작속도 | 200MHz |
| 검증단계 | Silicon | 참여공정 | SB130-2601 |
| IP개요 | This IP is a high-performance NMOS low-dropout (LDO) regulator designed for stable on-chip power delivery in SoC applications. It achieves high PSRR and robust loop stability over a wide load-current range using a multi-stage error amplifier and a PVT-insensitive control-voltage generator (CVG). A load-current sensing (LCS) circuit and domino-like buffer (DLB) dynamically adjust the regulator operation to provide fast transient response. The NMOS pass transistor reduces gate parasitic capacitance, enabling efficient high-speed gate control under rapid load variations. The proposed architecture supports stable operation with a small on-chip output capacitor, making it suitable for highly integrated SoC power-management systems. |
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