| IP명 | Power-Gating-Enabled SRAM Architecture with Sequence-Based Control for Low-Power NPU Systems | ||
|---|---|---|---|
| Category | Mixed | Application | 메모리 |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 10MHz |
| 검증단계 | Silicon | 참여공정 | SF028-2601 |
| IP개요 | A power-efficient SRAM reliability enhancement technique is proposed to effectively correct memory errors. The proposed scheme improves data integrity while supporting low-power memory operation with reduced energy overhead. As a result, it can contribute to lowering overall SRAM power consumption while maintaining reliable operation. |
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