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  Dear,   dc_shell  is operating well, there is no problem&nb..

 Okay. Thankyou very much.   [선혜승]님의 글 ========================..

  Hello    Alll errors are can be waived, you could finish now ab..

--EDA Tool정보-- EDA Tool 명(SCL/LCU/MGLS 포함) : Design Compiler EDA Tool 버전(S..

  Hello   You should upload the log file here  You can brows..

--EDA Tool정보-- EDA Tool 명(SCL/LCU/MGLS 포함) : Design Compiler EDA Tool 버전(S..

  Hello  1. Capture the message after ifconfig in your license server&n..

 답변 감사드립니다. 현재 이런 상태입니다.  spectre 하고 XCELIUM이 서로 ..

현재 상황이 정확히 파악되지 않아 두 가지 방법을 알려 드립니다. 1. 에러 메시지에 나..

답변 감사드립니다. 아래의 그 외 옵션 적용결과 동일하게 시뮬레이션이 안되고 있습니..

해당 내용만으로는 원인 파악이 어렵습니다.  메시지에 있는 것처럼 log 파일을 확..

 답변 감사드립니다. 현재 ADE -5021 Error 및 ADEXL 5069 Error가 발생하고 있는..

몇 가지 내용을 알려 드리니 확인해 보시기 바랍니다. 1. ADE-5021 관련   &..

Hi, I'm HuyDo from Kyunghee University with MPW8002, I have 2 problems as describ..

  Hi The maximum density needs to be addressed. Otherwise, it will look like..

  Thank you so much I'm following your suggestions for the problems. HereBy..

  Hi, Following your instructions, I added some more parameters in the Reset..

  Hello  I have uploaded the updated calview file  Look at the yo..

   It's working fine now. Thank you for your supports   [Sun Hye-..

Hello,   It seems to be caused By a problem with the contents of the /etc/ho..

영문제목 : DC motor driving By implementing ASM chart on Xilinx FPGA 개요 : Xilin..

As “Internet of Things (IoT) or “Smart Object” networks are becom..

IP Name Anti-harmonic Fractional-ratio Frequency Multiplying Delay-Locked Loop IP..

An all-digital frequency multiplying delay-locked loop (FMDLL) that provides both p..

The LPDDR SDRAM memory controller with the AHB interface is used to control LPDDR S..

Internet of things (IoT) is one of the most discussed topics and a growing trend to..

Internet of things (IoT) is one of the most discussed topics and a growing trend to..

Internet of things (IoT) is one of the most discussed topics and a growing trend to..

IC Design Education Center(IDEC)   ..

Digital Background Calibration By dividing & swapping capacitor to reduce the effec..

Category Analog & Mixed Signal > Timing/Clock Circuit > Others Description ..

Category Analog & Mixed Signal > Power Management Circuit > DC-DC Converter > (Ty..

Category Analog & Mixed Signal > Timing/Clock Circuit > Others Description ..

Category Analog & Mixed Signal > Timing/Clock Circuit > PLL > (Output Freq.) Over..

Category Analog & Mixed Signal > Data Converter > A/D Converter > (Resolution) Un..

Category Analog & Mixed Signal > Timing/Clock Circuit > PLL > (Output Freq.) Over..

IC Design Education Center(IDEC) 제22회 한국반도체학술대회 Chip Design Contest..

Byte Data Read - Write: Erase/Program Reference Voltage - VREF_CP: 1.042V~1.125V..

AXI4 protocol converter converts the protocols for communication between t he AXI4..

8x8 AXI3 Interconnect matrix has five independent channels of communicati on using..