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 *WARNING* The directory: '/CAS2/sensor2017/Work/AMSTEST_DIGITAL' does not exi..

첫번째 warning 은 cds.lib 파일에는 define 되어 있으나 directory 가 실제로 없어서 뜨..

library manager 창에 있는 곳에는 AMSTEST_DIGITAL 가 없어서.  lib에 있는 ..

해당 에러는 무시해도 됩니다. calibre Verification 을 할 때 export from layout..

     말씀하신대로 하여도 계속 오류가 뜹니다.    [조인..

첨부한 파일과 글만으로는 원인을 파악하는데 어려움이 있습니다. 개인 PC 에서 원격접..

   설치하였습니다.  5369 9698 6749   [조인신 ]님의글 ======..

코드 번호가 맞지 않습니다. 아래 메일로 전화번호 송부 바랍니다.   조인신 : i..

Hi,   Thank you very much for the answer. I have followed the instruct..

Hi,   1. install rpm command : yum install *lsb*    or&nbs..

Hi,   Once again thank you very much for the answer. But, I've tried the co..

Hi,   See the below page. https://software.intel.com/en-us/articles/flexlm-..

 Thank you very much for the answer. I've tried the command that you recommen..

My name is Dzuhri from Prof. Lee Sang0Gug's Laboratory. I'm installing the Cadence..

  Hi    1. Re-get  LCU first  Download LCU04.25.001.ta..

 Hi,   Thank you very much for the answer. I have followed the in..

  Hi,   Thank you very much for the answer. I have followed the ..

  [root@iic 64bit]# ./lmstat -a -c Cadence20180629.txt lmstat - Copyright (c)..

log 파일의 내용 중 HostID of the License Server: "38d547013bd0 38d547013bcf" ..

network 카드가 두개네요 [root@iic ~]# ifconfig -aenp7s0: flags=4163<UP,BROADCAS..

영문제목 : DC motor driving By implementing ASM chart on Xilinx FPGA 개요 : Xilin..

As “Internet of Things (IoT) or “Smart Object” networks are becom..

IP Name Anti-harmonic Fractional-ratio Frequency Multiplying Delay-Locked Loop IP..

An all-digital frequency multiplying delay-locked loop (FMDLL) that provides both p..

The LPDDR SDRAM memory controller with the AHB interface is used to control LPDDR S..

Internet of things (IoT) is one of the most discussed topics and a growing trend to..

Internet of things (IoT) is one of the most discussed topics and a growing trend to..

Internet of things (IoT) is one of the most discussed topics and a growing trend to..

IC Design Education Center(IDEC)   ..

Digital Background Calibration By dividing & swapping capacitor to reduce the effec..

Category Analog & Mixed Signal > Timing/Clock Circuit > Others Description ..

Category Analog & Mixed Signal > Power Management Circuit > DC-DC Converter > (Ty..

Category Analog & Mixed Signal > Timing/Clock Circuit > Others Description ..

Category Analog & Mixed Signal > Timing/Clock Circuit > PLL > (Output Freq.) Over..

Category Analog & Mixed Signal > Data Converter > A/D Converter > (Resolution) Un..

Category Analog & Mixed Signal > Timing/Clock Circuit > PLL > (Output Freq.) Over..

IC Design Education Center(IDEC) 제22회 한국반도체학술대회 Chip Design Contest..

Byte Data Read - Write: Erase/Program Reference Voltage - VREF_CP: 1.042V~1.125V..

AXI4 protocol converter converts the protocols for communication between t he AXI4..

8x8 AXI3 Interconnect matrix has five independent channels of communicati on using..