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IP명 Noise incremental Delta-Sigma Analog Front End with Closed-Loop Chopper Stabilization for Capacitive Microsensors
Category Analog Application 연구
실설계면적 3.8㎛ X 3.8㎛ 공급 전압 3.3V
IP유형 Hard IP 동작속도 10MHz
검증단계 Silicon 참여공정 MS180-1805
IP개요 A low-noise incremental Delta–Sigma Capacitance to Digital Converter(CDC) integrated circuit (IC) for capacitive microsensors is presented. In the conventional CDC, two-step conversion schemes including capacitance to voltage converter and voltage to digital converter are generally used. The presented Delta-Sigma CDC can convert the capacitance changes to the digital codes directly. The Delta-Sigma schemes are widely used for low noise applications due to the Delta-Sigma modulator’s ability to reduce in-band white noise by the inherent noise shaping characteristic. The low frequency colored noises such as flicker (1/f) noises still remain. In order to reduce the low frequency colored noise component, a chopper stabilization technique is exploited to the SC integrator of the Delta-Sigma CDC. The integrated circuit is implemented in a 0.18-μm standard CMOS process. The proposed incremental Delta–Sigma CDC consumes 1.12-mW of power from a 3.3-V supply at a sampling frequency of 500-kHz.
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