| IP명 | 전력노이즈의 I/O회로 및 인버터체인 지터에 대한 영향 정밀분석 회로 | ||
|---|---|---|---|
| Category | Analog | Application | 연구 |
| 실설계면적 | 3.8㎛ X 3.8㎛ | 공급 전압 | 1.8V |
| IP유형 | Hard IP | 동작속도 | 1GHzHz |
| 검증단계 | Silicon | 참여공정 | MS180-1704 |
| IP개요 | Power supply noise induced jitter (PSIJ) at inverter chains is analytically modeled. Accuracy of the proposed analytical model of PSIJ at inverter chains will be validated by jitter measurement with different power supply noise configurations. In this analog-type design, several inverter chains with supply power of 1.8 V and maximum operating frequency of 800 MHz are designed based on 180nm Magna/Hynix process. In addition, onchip power distribution networks without and with on-chip voltage regulator module provide different on-chip power supply noise characteristics, which enable validation and in-depth analysis of PSIJs at variety situations. |
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- 레이아웃 사진 -
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