| IP개요 |
we propose a reliable low-power adder and multiplier design using replica circuits for near-threshold voltage (NTV) operation. Our replica circuits adopt algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. |
