| IP개요 |
we propose a low latency IFFT (Inverse Fast Fourier Transform) architecture for LTE in 3rd Generation Partnership Project (3GPP). Proposed method reduces the latency of IFFT through input reordering. The latency is reduced by around 42 % in the proposed IFFT processor. The proposed method is suitable for next generation mobile communication system which requires high-speed data processing. We implement the proposed IFFT processor using MagnaChip/SK Hynix 180 nm CMOS process. The circuit type of the proposed crcuit is digital. The supply voltage is 1.8V and the maximum operating frequency is 20 MHz |
