| IP명 | A Cryptographic Processor Implementing Multiple Block Cipher Algorithms of PRESENT/ARIA/AES | ||
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| Category | Digital | Application | Crypto_processor |
| 실설계면적 | 3.8㎛ X 3.8㎛ | 공급 전압 | 3.3, 1.8V |
| IP유형 | Hard IP | 동작속도 | 55MHz |
| 검증단계 | FPGA | 참여공정 | MS180-1604 |
| IP개요 | A design of the cryptographic processor which implements multiple block cipher algorithms including PRESENT, ARIA, and AES. | ||
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