| IP개요 |
This work proposes 1Gb/s All-Digital Clock and Data Recovery (ADCDR) circuit using injection architecture and new PD name XBBPD. The proposed injection locking architecture have advantages that are fast locking and small layout size. Also the new PD(phase detector) is name XBBPD that have an advantage is that phase and frequency are detected by using that in same time. So the proposed circuit is dual loop(one is the injection lock PLL(IL-PLL) and frequency lock loop(FLL) using XBBPD). This architecture have advantages those are new type XBBPD and fast locking time in IL-PLL. The proposed ADCDR is composed injection locking PLL and FLL loop. The IL-PLL is composed of pulse generator and injection DCO. The PLL is composed of XBBPD, gain controller, digital loop filter (DLF) and DCO. This architecture is based on mixed signal circuit of 0.18um CMOS Process and the supply voltage is 1.8V |
