| IP개요 |
The advent of the Internet of Things has given rise to the branch of lightweight cryptography to safe guard data on pervasive devices. A number of lightweight proposals meet the hardware area requirements but falls short on the latency requirements. We therefore implement a new lightweight block cipher that is specifically designed to have a small hardware footprint and also high throughput. The cipher consists of a 128 bit key that takes 8 rounds to encrypt a block of 64 bit data. It uses a Feistel structure together with a substitution box and a one stage omega permutation network permutation box. The cipher was verified by designing a smart phone application that sends a plaintext through Bluetooth communication to the encryption/decryption core on HBE-SoC-IPD test board equipped with Virtex4 FPGA device. The encryption/decryption core synthesized to 300 slices at 337 MHz maximum clock frequency using Xilinx ISE 14.3. The design will further be synthesized using Magna Chip Semiconductor/SK Hynix 180nm process.
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