| IP개요 |
In this paper, an energy-efficient successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The total power consumption of the CDC is 86.4 μW with a 1.8-V supply. The SAR CDC achieves a conversion time of 1.125 ms. |
