| IP개요 |
This project proposes a digital baseband processor that can endure severe burst errors in the high-speed near-filed wireless communications. In order provide an energy-efficient and low-latency baseband processing, which is necessary for the commercial product including wireless virtual reality (VR) solutions, the conventional iterative error correction code (ECC) associated with power-hungry ADCs is replaced to the simple but effective hard-decision ECC. To maximize the error correcting capability, we carefully analyze the channel condition of the near-field wireless communication systems and design the optimal block interleaver to spread out burst error patterns to be corrected by the proposed simple ECCs. As a result, the proposed baseband processing can recover up to 1080 consecutive errors in a data frame of 100K bits. By eliminating the time consuming high-resolution ADCs and iterative decoding scheme, furthermore, the proposed method can effectively reduce communication latency, which can be applied to the zero-latency applications. All the functionalities of the proposed work are already verified by software simulations using MATLAB and verified by RTL simulation using Simvision. If the proposed system is fabricated in a 65nm CMOS process, this system could be the first realization for the zero-latency wireless multimedia solution. |
