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IP명 True Random Number Generators based on Chaotic Circuits
Category Analog Application IoT security-related applications
실설계면적 3.8㎛ X 1.9㎛ 공급 전압 3.3V
IP유형 Hard IP 동작속도 1MHz
검증단계 Silicon 참여공정 MS180-1802
IP개요 In this work, we design three CMOS TRNGs based Tent shape/V-shape/N-shape map
chaotic circuits. First, the V-like map, Tent-like
and N-shape maps using stroboscopic sampling method and
their chaotic behaviors are analyzed with the help from
numerical Mathematica simulation software. The robustness of
the designed chaotic maps is also confirmed by analyzing
Lyapunov exponent diagram. The simulation results confirm the
proposed scheme. Furthermore, the compact size, low power
consumption and the robustness of chaos generation of the
designed chaotic circuits with variation of fabrication
parameters thus recommending a solution of designing on-chip
true random number generators for the IoT security-related
applications
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