| IP개요 |
This paper presents a first-order delta-sigma (ΔΣ) capacitance-to-digital converter (CDC) with low noise character-istics and reconfigurable resolution of 12-to-16-bit. The pro-posed ΔΣ CDC is implemented as a first-order ΔΣ modulator with a switched capacitor (SC) integrator and comparator. The resolution can be reconfigured by the accumulator using recon-figurable 12-to-16-bit up-counter. The ΔΣ schemes are widely used for low noise applications due to the ΔΣ modulator’s ability to reduce in-band white noise by the inherent noise shaping char-acteristic. The low frequency colored noises such as flicker (1/f) noises still remain. In order to reduce the low frequency colored noise component, a chopper stabilization technique is exploited to the SC integrator of the ΔΣ CDC. The proposed ΔΣ CDC also controls the offset calibration capacitors adjusting the DC offset. This is caused by a capacitor mismatch due to process variation and parasitic capacitor of the input capacitive sensor. The total current consumption for 16-bit ΔΣ CDC is 141μA in the 1.8V supply. |
