| IP명 | High speed CMOS Direct Digital Frequency Synthesizer with nonlinear Digital-to-Analog Converter | ||
|---|---|---|---|
| Category | Mixed | Application | Communications |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | Hard IP | 동작속도 | 2GHz |
| 검증단계 | Simulation | 참여공정 | SS65-1802 |
| IP개요 | A direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 1 GHz is presented. This work includes three design methods that enhance the performance of a DDFS. First, a pipelined PACC structure is employed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9-bit amplitude resolution is capable of producing a minimum spuriousfree dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 65-nm CMOS. |
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