| IP명 | Design of High speed Pipelined sub-ADC for TI-ADC. | ||
|---|---|---|---|
| Category | Analog | Application | wideband full digital receiver |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | 동작속도 | 100000000Hz | |
| 검증단계 | Silicon | 참여공정 | SS65-1802 |
| IP개요 | Design of high-speed Pipelined sub ADC to be used in TI-ADC for wide-band full digital receiver application. | ||
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