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IP명 300 GHz 주파수 대역에서 동작하는 송수신 시스템 설계
Category Analog Application Communication
실설계면적 4000㎛ X 4000㎛ 공급 전압 1.5V
IP유형 Hard IP 동작속도 300GHz
검증단계 Simulation 참여공정 SS65-1803
IP개요 Various circuits for terahertz communication systems designed with CMOS technology is reviewed. This paper presents 300 GHz power amplifier, 300 GHz Phase Locked Loop Samsung 65nm CMOS technology. The 6stage common source power amplifier exhibits a peak gain of 11 dB with 16 GHz bandwidth based on the measured results. The 300 GHz voltage-controlled oscillator shows that 3rd harmonic output signal of which output power is around -8.6 dBm varies from 278 GHz to 283 GHz in simulation. The total power consumption is 200 mW from Vdd = 1.5 V with analog design.
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