| IP명 | An Active Ground Bounce Reduction Scheme for Simultaneously Switching Output Buffers | ||
|---|---|---|---|
| Category | Analog | Application | Signal integrity |
| 실설계면적 | 3.8㎛ X 3.8㎛ | 공급 전압 | 3.3V |
| IP유형 | 동작속도 | 1 GHz | |
| 검증단계 | Silicon | 참여공정 | MS180-1901 |
| IP개요 | Design and analysis of an Active Ground Bounce Reduction Scheme for Simultaneously Switching Output Buffers | ||
- 레이아웃 사진 -
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