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"한국 반도체산업의 경쟁력"

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IP명 A fast transient digital-LDO with 99.9% current efficienxy
Category Analog Application PMIC
실설계면적 4㎛ X 4㎛ 공급 전압 1V
IP유형 Hard IP 동작속도 20MHz
검증단계 Silicon 참여공정 SS28-1901
IP개요 This paper presents a fully digital, current efficient and fast transient response digital low drop-out regulator to be used in multi-voltage domains levels for on chip delivery networks. A boost mechanism is embedded with the normal loop of operation which achieves the fast transient response in current transients. The structure reveals the efficient load regulation with the reduced ripple effects. The proposed structure is designed in samung-28nm CMOS process. The simulated response shows the transient response of 45ns with 10mA of load current. With this condition, it achieves the peak current efficiency of 99.9%. The design parameters of proposed digital-LDO are supply voltage 1V, maximum operating frequency 20MHz, complete digital architecture.
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