|IP명||A 50 M–1 GHz 2.3 dB NF Noise-Cancelling Balun-LNA Employing a Modified Current Bleeding Technique and Balanced Loads|
|실설계면적||3.5㎛ X 3.5㎛||공급 전압||1.2V|
|IP개요||A new noise-cancelling method that employs a modified current-bleeding (CBLD) technique and balanced loads is presented by developing a design for a low-noise and high-linearity balun-low-noise amplifier (LNA) for broadband applications. The basic common-gate (CG) – common-source (CS) balun topology cannot achieve a noise figure (NF) of less than 3 dB. Thus, a practical topology containing a CS transistor of which the transconductance is N times larger than that of the CG transistor and a CS resistor of which the resistance is N times smaller than that of the CG resistor is often used to decrease the NF. However, unsymmetrical load resistors cause a gain and phase imbalance at the differential output. The proposed modified CBLD technique enables the balun-LNA to achieve differential balanced output, low noise, and low second-order distortion characteristics.
The proposed balun-LNA is implemented in 65-nm CMOS technology and covers the frequency range of 50 MHz to 1 GHz. It achieves a voltage gain of 30 dB, a S11 of less than −10 dB, an OIP3 of 25.9 dBm, and an OIP2 of 50.6 dBm. The minimum NF
is 2.3 dB whereas the average NF is 2.63 dB across the whole band. It operates at a nominal supply voltage of 2.2 V with bias currents of 9 mA. The active die area is 0.0448 mm2.
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