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홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

IDEC에서 설계인력양성의 발판을 마련하겠습니다.

IP명 A Reliable SoC Design using Replica Circuits for Near-Threshold Voltage Operation
Category Mixed Application 신호처리
실설계면적 4㎛ X 4㎛ 공급 전압 0.5V
IP유형 Hard IP 동작속도 28.57MHz
검증단계 Silicon 참여공정 SS65-2001
IP개요 In this paper, we propose a reliable low-power adder and multiplier design using replica circuits for near-threshold voltage (NTV) operation. Our replica circuits adopt algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. For a 32 × 32 bit ANT adder implementation, a 8 × 8 bit replica adder is used which increases the clock speed by 33.3% compared to normal worst case clock speed, with marginal error performance degradation.
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