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IP Library

홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

IDEC에서 설계인력양성의 발판을 마련하겠습니다.

IP명 Low Power Multi-Channel 12-bit SAR A/D Converter for Biosignal Processing
Category Analog Application ADC
실설계면적 4㎛ X 4㎛ 공급 전압 1.2V
IP유형 Hard IP 동작속도 20MHz
검증단계 Simulation 참여공정 SS65-2001
IP개요 The proposed SAR ADC consists of one main 12-bit SAR ADC, an assistant 12-bit SAR, and a 12-bit output register to generate the final 12-bit binary codes. The main 12-bit SAR ADC (ADC1) is composed of a preamplifier to block the kick-back noise of the clock signal, a low power latched comparator to generate data that will be fed to the 12-bit SAR logic, a 12-bit control logic to assist the 12-bit SAR logic, and two 12-bit fully differential C-DACs with the unit split capacitor to be controlled by the 12-bit SAR logic. The assistant 12-bit SAR ADC (ADC2) consists of the same architecture as the main ADC, except the 6-bit SAR logic and 6-bit control logic to control the 6-bit LSB switches of the 12-bit CDAC. Since the 6-bit MSB switches of ADC2 shown in the shaded area in Fig. 1 are controlled by the 6-bit MSB of ADC1, the 36 differential switches of C-DAC in the ADC2 can be eliminated with respect to those of C-DAC in the ADC1. Elimination of 36 differential switches results in reduction of more than 50% switching energy of the proposed ADC with respect to the conventional ones. Fig. 2 illustrates the timing diagram of the clock, reset 1, reset 2, Q1, and 12-bits.
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